Essay: Addressing in z9 Mainframes
Essay: Addressing in z9 Mainframes
The z/Architecture of System z9 Mainframes extends the capability of the system by implementation a wider memory addressing and instruction set. Thru the use of 64-bit addressing and registers, the System z9 Mainframe allows the application to exploit latest technologies with increased performance through a larger pool of resource, while still remaining backward compatible for execution of 32-bit applications.
6.1. 64-Bit Registers.
By extending the width of all registers to 64-bits, IBM has addressed the requirement of today’s businesses which increasingly require a system which could access and address objects with a size larger than two gigabytes. Through 64-bit addressing, the System z9 has offered new capabilities to application developers, which would now enable them to scale their applications to new heights.
6.2. Instruction-set Architecture.
The Architecture of the instruction set in System z9 is designed to keep the operating mode and operand width separate. That is, it is possible to used 64-bit addressing with 32-bit arithmetic operations and vice versa on a System z9 Mainframe. This allows maximum flexibility to application developers which can now choose how and when to take advantage of 64-bit capabilities of the system for optimized application performance. However, this has introduced a large number of instructions to perform the 64-bit equivalent of its 32-bit counterpart. These instructions are separate from those instructions which allow for 32-bit and 64-bit operands to be used together. Almost all instructions in System z9 instruction sets are non-modal, that is, instruction mode in System z9 is defined by instruction operation code and not by current addressing mode. However, it also has several model instructions, which change their behavior according to the current addressing mode.
6.3. Memory Addressing
The System z9’s z/architecture uses a simplistic design from the virtual memory address. It implements a hierarchy of regional tables and segment tables in order to perform translation of virtual memory addresses to real storage addresses. It uses two bits in address-control-element, which is the anchor of address translation in z/Architecture for real as well as virtual memory, to indicate which table will be used for translation of an address (Plambeck, Eckert, Webb, & Rogers, 2002).
7. Hardware Management Console and Support Element
The Hardware Management Console (HMC) that comes with the System z9 Mainframe provides a single hardware control point that can be used to create and modify the configuration as well as perform updates of the system. These activities are performed through the use of two available interfaces, a traditional interface which has the same appearance as the previous HMC consoles, and a new tree interface which implements a hierarchy between the different elements of the System z9 Mainframe. The System z9 HMC is accessed through a web browser and allows full control of the system. This new approach is System z9 Mainframe is much less LAN intensive than previous versions of HMC which used high bandwidth applications such as Desktop on Call. The System z9 Mainframes also have Support Elements (SE). These are two IBM Thinkpads which are located in the system covers in the Z frame of the System z9 Mainframe. One of these support elements is designated as primary while the second one serves as a backup. These support elements are only meant to be used by IBM Service Representatives; however, it may be used to manage the system in case of HMC failure. A LAN connection may exist between HMC’s and SE in order to provide automatic redundancy and sharing of tasks (White, Injey, Chambers, Gasparovic, Hamid, Hatfield, Hewitt, Jorna & Kappler, 2007).
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