Essay: Channel Subsystem (CSS) of z9 Mainframes

Essay: Channel Subsystem (CSS) of z9 Mainframes
April 13, 2011 Comments Off on Essay: Channel Subsystem (CSS) of z9 Mainframes Academic Papers on Information Technology,Sample Academic Papers admin

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In System z9 Architecture, the Channel Subsystem controls the communication of external as well as internal channels through which System z9 devices and units are controlled. It provides Mainframe with a communication path through channel connections with which the Mainframe can communicate with the external devices. The main feature of the Channel Subsystem is that it allows for the channel I/O operations to be performed independently of other operations being performed by the central processors.

5.1.      Multiple CSS Concept

A single System z9 Mainframe can have up to four Channel Subsystem (CSS).The concept behind Multiple Channel Subsystem is, to provide the ability for more than 256 CHPIDs to be defined in System z9 Mainframes. As the System z9 Mainframes have been designed to offer significant processing power, I/O connectivity and memory sizes, the scaled up concept of CSS from previous generations, supports greater number of channels hence the System z9 Mainframe is able to connect to a large number of I/O devices as well as support up to a maximum of 60 logical partitions.

5.2.      Multiple CSS Structure

The System z9 Mainframes can have up to four CSSs which allows up to 256 channels to be defined in the systems. This definition of channels is not bound to a single book and each CSS can define resources that are physically connected to any STIs on any book of the System Z9 CEC cage. Each System z9 Mainframe is required to have at least one CSS. This is necessary to define logical partitions as they are only defined and associated to a CSS and cannot exist without it. All CSS Images are stored in a single I/O configuration data set (IOCDS). This IOCDS is initialized and loaded into the Hardware System Area during the Power-on Reset.

Multiple SubChannel Sets (MSS)

The Multiple SubChannel Sets (MSS) is a new functionality that has been introduced with System z9 Mainframes. This functionality allows for the definition of sub-channels within the defined channels and grouping these of subchannels into sets, with 64k subchannels in each set. By implementing MSS functionality, IBM has removed the restriction of only 64k addresses in previous systems and has enabled the System z9 Mainframe to access a large number of devices using parallel access technologies such as Parallel Access to Volume (PAV) (White, Injey, Chambers, Gasparovic, Hamid, Hatfield, Hewitt, Jorna & Kappler, 2007).

5.3.      MIDAW

The System z9 Mainframes implements a new data gathering/scattering facility which known as Modified Indirect Data Address Word (MIDAW). In earlier generations, an Indirect Address Word (IDAW) was used to specify the data address that was used for an I/O operation in a virtual environment. The design of IDAW required all IDAWS in a list maintained in memory to point to first byte of a memory page, except for the first and last one which could point to any address within a memory page. This limited the usability of IDAWs to only buffering of a sequential record. Data chaining was used to process I/O data blocks with a more complex structure with portions of data existing in separate buffer areas. However, with evolution in technology and increasing links speeds, the data chaining techniques have become less efficient due to involvement of control unit processing, exchanges and switch fabrics. MIDAW, however, allows for efficient scattering and gathering of data by exploiting discontinuous use of storage locations within the memory during an I/O operation. It allows for storage and addressing of memory chucks of uneven sizes which makes it possible to efficiently distribute small chunks of data into separate buffers, as compared to the larger even chucks used in data chaining. This way, MIDAW is not only able to improve FICON performance through extended format datasets, but also improves channel utilization and I/O response time (Ogden, Gasparovic, & White, 2007).

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