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Essay: Enterprise Computing
Essay: Enterprise Computing
Describe in detail the following components.
a) Hierarchy of microprocessors.
b) What features is there that System i5 has been described as microprocessor excellence?
c) How is System i5 integrated with Microsoft Windows operating system?
d) What is cross-site mirroring? (5 points)
Hierarchy of Microprocessors in System i5 Series
The System i55 Series is designed by keeping the business environment in mind. Business environments are often characterized by their being I/O-intensive rather than computer-intensive. The microprocessor hierarchy of System i55 not only provides outstanding performance in the business environment, it also provides an exquisite way to integrate diverse environment into a single, harmonious client solution. The architecture of System i55 servers is designed in such a way that the microprocessors that handle a particular I/O devices are accommodated on I/O cards that fit into slots on system buses. High performance is achieved through the use of several individual high-performance microprocessors, I/O devices and interconnects technologies. The enabler of this high performance on System i55 servers is the POWER5 distributed switch that supports enormous bandwidth between processors, cache, memory and the I/O devices. During the program run, its execution is handled by POWER5 enabled microprocessors while the movement of data is handled by the high performance I/O adapter and I/O processors. The data moves between the I/O tower and to Integrated xSeries Adapter PC server across HSL at 2 GB/s.
In IBM @server Model 520 without L3 cache the POWER5 chip is packaged into cost-effective Single Chip Module (SCM) package while on all other servers, the POWER5 chip is packaged with L3 cache into a single cost-effective Dual Chip Module (DCM) package. Each POWER5 processor card contains a single DCM which contains a POWER5 chip, a 36 MB Level 3 Cache and its memory. The multichip modules (MCMs) have eight processors each. In each MCM, there are four physical copper SOI chips with two processor cores. Each of the core is symmetric multi-threading capable which appears to the operating as two separate processors. Each chip has two processor made from 276 million transistors and runs at a speed beyond 1.5 GHz. The MCM is the building block of the system. It is only available with four chips, each having its own L3 cache attached. The processor on a single chip also has L2 and L3 cache resources attached to the module (144 MB per MCM).
A single large System i55 configuration can have well over 650 processors. The main system processor complex can handle the request for reading and writing of data by delegating the request to the processor handling that particular I/O while the rest of the system can continue executing the program (Bresenham, McClymont, Powers, Reinhardt, & Watson, 2006).