Essay: Hardware Elements of z9 Mainframe

Essay: Hardware Elements of z9 Mainframe
12/04/2011 Comments Off on Essay: Hardware Elements of z9 Mainframe Academic Papers on Information Technology,Sample Academic Papers admin

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The IBM z9 series Mainframe offers significant increase in opportunity of Mainframe consolidation as well as in system scalability by introducing a Book based architecture. A Book is the core unit of System z9 series computer responsible for processing of data as well as control of functionalities provided by the System z9 Mainframe. The System z9 Mainframe series can support up to 4 books depending on its model.

Each book consists of a Multiple Chip Module containing Processor Units (PU), Physical memory and Memory Bus Adapter Fanout Cards.  Each PU in the MCM owns a 512KB store through cache, which is equally divided for instructions and data storage. The Book also contains a number of chips which provide control and co-ordination between different components. The co-ordination between PU, Memory Controller and the MBAs takes places through the Storage Controller (SC) chip while the System Controller chip controls the MBA fanout cards used to provide connectivity to the I/O cage. The Memory Controller, controls a large 40 megabytes Level 2 cache, and is also responsible for communication between books in ring topology, connecting the four books through two loops, called the ring structure.

3.1.1.     Multiple Chip Module (MCM)

The Multiple Chip Module (MCM) is the heart of the Book.  It contains all the processor units, Cache Memory, Clock, coherency control circuitry as well as Memory Storage controller. All PUs except one can be used as characterized for particular use or can operate as uncharacterized. Each MCM has one PU which is always used as System Assistance Processor.  No PU is reserved as spare (White, Injey, Chambers, Gasparovic, Hamid, Hatfield, Hewitt, Jorna & Kappler, 2007).

3.1.2.     Processor Units (PU)

The Processing Unit (PU) in System z9 architecture is the unit responsible for executing instructions. Each PU is a super-scalar processor which able to execute three instruction per cycle. Each PU also has two Level 1 caches of 256kB each for instructions and data. Each cache is a four-way set associative and has a 512 entry capacity Translation Lookaside Buffer. There is also a secondary TLB with 512 entries at the first virtual memory segment level which is 16-way set associative. A four way set associative branch history table, with capacity of 8K entries also enhances the address translation function.

3.1.3. PU Characterizations

The internal Mainframe functions of the Mainframe, characterize the PUs into a number of types during the Power-on reset function. These characterizations are:

Central Processor (CP): The standard processor characterization for use with an operating system or with applications.

Internal Coupling Facility Processor (ICF), which characterize a processor for Internal Coupling Facility.

Integrated Facilities for Linux: dedicated processor for with use with Linux and for z/VM processing done to support Linux.

System Assistance Processor (SAP): Characterize a CPU for increasing I/O capacity of the Mainframe.

System z Application Assist Processor (zAAP): Special characterization of a processor used for executing JVM functions only.

System z9 Integrated Information Processor (zIIP): characterizes a processor for specialized function. Once characterized, zIIP processor cannot be used for general z/OS work.

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